1. Technical Field
The present invention relates to an image processing circuit and a multi-function apparatus having the image processing circuit.
2. Related Art
Images input from a scanner in a multi-function apparatus are often processed in the unit of frames. The image process is performed by scanning frame images stored in a memory.
In general, a DRAM (Dynamic Random Access Memory) is used as the memory storing the frame images. When it is intended to read data from the DRAM and a row address is specified, contents of a memory cell (one page) corresponding to the row are loaded to a buffer in the DRAM. The DRAM requires time for reading data from the memory cell, but reads the data stored once in the buffer at a high speed. An access to DRAM using this characteristic is called page-mode access. In the page-mode access, plural data can be read from the buffer at a high speed while changing a column address after once specifying the row address.
JP-A-2002-99876 discloses an image process of sequentially and successively scanning (hereinafter, referred to “two-dimensional scanning ”) pixels located neighborhood in a frame image stored in the memory.
However, the frame image stored in the memory is generally stored so that two-dimensionally arranged pixels correspond to two-dimensional addresses in the memory. Accordingly, when the frame image stored in the DRAM is two-dimensionally scanned, it is often scanned in such an order to overlap with a page boundary to make the page-mode access difficult. As a result, it is much time to two-dimensionally scan the frame image.